1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a split gate flash memory and manufacturing method thereof.
2. Description of the Related Art
Among the various types of non-volatile memory products, flash memory device is a memory device that has been widely used inside personal computer systems and electron equipment. In the flash memory, data can be stored, read out or erased many numerous times and stored data are retained even after power is cut off.
Typically, the floating gate and the control gate of a flash memory cell are fabricated by doped polysilicon. Furthermore, the floating gate and the control gate are isolated from each other through a dielectric layer and the floating gate and the substrate are isolated from each other through a tunneling oxide layer. To perform a data write/erase operation on the flash memory, a biased voltage is applied to the control gate and the source/drain regions. As a result, electrons are injected into the floating gate or pulled out from the floating gate. To read data from a flash memory, an operating voltage is applied to the control gate so that the charging state of the floating gate will effect the ‘on’ or ‘off’ state of the channel underneath. Consequently, the ‘on’ or ‘off’ state of the channel can be used to determine if a ‘0’ or ‘1’ data bit is read out.
Because the quantity of electric charges expelled from the floating gate when erasing data from the aforementioned flash memory is difficult to control, too many charges may be expelled from the floating gate leading to the floating gate having a net positive charge, the so-called ‘over-erasing’. If the degree of over-erasing is severe, the channel underneath the floating gate may continue to be conductive even though no operation voltage is applied to the control gate. As a result, errors in reading from the flash memory may occur.
To resolve the over-erasing problem, a flash memory with a split gate structure has been developed. FIG. 1 is a schematic cross-sectional view showing the structure of a conventional split-gate flash memory cell. The flash memory cell in FIG. 1 has a structure including a tunneling dielectric layer 102, a floating gate 104, an inter-gate dielectric layer 106 and a select gate 108 sequentially formed over a substrate 100. Aside from covering the floating gate 104, a portion of the select gate 108 also extends to cover an area above the substrate 100. The select gate 108 is isolated from the substrate 100 through a select gate dielectric layer 110. The source region 112 is formed in the substrate 100 on one side of the floating gate 104. The drain region 114 is formed in the substrate 100 on the same side as the extension of the select gate 108. With this setup, even when the over-erasing problem is so severe that the channel underneath the floating gate 104 remains open in the absence of an operating voltage to the select gate 108, the channel underneath the select gate 108 is still maintained in the shut-down state. Thus, the drain region 114 and the source region 112 are cut off from each other and reading error is prevented.
However, a split gate structure needs a larger area to accommodate the split gate so that the size of each memory cell has to increase. Thus, the memory cell with a split gate structure must occupy a larger area compared with the memory cell with a stacked gate structure. In other words, the level of integration of the devices can hardly increase.
Furthermore, as the level of integration of integrated circuits continues to increase through miniaturization, the dimension of each memory cell can be reduced by shortening the length of the gate. Yet, a shorter gate length will lead to a reduction of the channel length underneath the gate. With a shorter channel, the chance of having an abnormal punch through between the drain region and the source region is increased during memory cell programming. Ultimately, the electrical performance of the memory cell will be seriously affected.